Publications and Talks
Conference Papers 
Journal Papers 
Book Chapters 
Technical Reports 
Talks
Conference Papers
2008
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FPGA Design Framework for Partial Run-Time Reconfiguration
C. Conger, A. Gordon-Ross. A. George. The International Conference on
Engineering of Reconfigurable Systems and Algorithms (ERSA), July 2008.
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Phase-Based Cache Reconfiguration for a Highly-Configurable Two-Level
Cache Hierarchy
A. Gordon-Ross, J. Lau, B. Calder. ACM Great Lakes
Symposium on VLSI (GLSVLSI), May 2008.
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A Table-based Method for Single-Pass Cache Optimization
P. Viana, A. Gordon-Ross, E. Baros, F. Vahid. ACM Great Lakes Symposium on
VLSI (GLSVLSI), May 2008.
pdf
ppt
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Smart-NICs: Power Proxying for Reduced Power Consumption in Network
Edge Devices
K. Sabhanatarajan, A. Gordon-Ross, M. Oden, M. Navada, and A. George.
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), April 2008.
pdf
ppt
2007
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A Self-Tuning Configurable Cache
A. Gordon-Ross, F. Vahid. IEEE Design Automation Conference (DAC),
July 2007.
pdf
ppt
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A One-Shot Configurable-Cache Tuner for Improved Energy and
PerformanceA. Gordon-Ross, P. Viana, F. Vahid, W. Najjar,
E. Barros. IEEE/ACM Design, Automation and Test in Europe (DATE),
April 2007. pdf
ppt
2006
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Configurable Cache Subsetting for Fast Cache Tuning
P. Viana, A. Gordon-Ross, E. Keogh, E. Barros, F. Vahid. IEEE Design
Automation Conference (DAC), July 2006.
pdf ppt
2005
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Fast Configurable-Cache Tuning with a Unified Second-Level Cache
A. Gordon-Ross, F. Vahid, N. Dutt. IEEE/ACM International Symposium on
Low Power Electronics and Design, August 2005.
pdf ppt
- A First Look at the Interplay of Code Reordering and Configurable Caches
A. Gordon-Ross, F. Vahid, N. Dutt. ACM Great Lakes Symposium on VLSI (GLSVLSI) April 2005.
pdf ppt
2004
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Automatic Tuning of Two-Level Caches to Embedded Applications
A. Gordon-Ross, F. Vahid, N. Dutt. IEEE/ACM Design, Design Automation and Test in Europe,
February 2004. pdf
ppt
2003
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Frequent Loop Detection Using Non-Intrusive On-Chip Hardware
A. Gordon-Ross, F. Vahid. IEEE/ACM International Conference on Compilers,
Architectures and Synthesis of Embedded Systems, October 2003.
pdf
ppt
2002
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Dynamic Loop Caching Meets Preloaded Loop Caching -- A Hybrid Approach
A. Gordon-Ross, F. Vahid. IEEE International Conference on Computer Design, September 2002.
pdf
ppt
2001
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A Self-Optimizing Embedded Microprocessor using a Loop Table for Low Power
F. Vahid, A. Gordon-Ross. IEEE/ACMInternational Symposium on Low Power Electronics and Design,
August 2001.
pdf
ppt
Journal Papers
2005
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Frequent Loop Detection Using Non-Intrusive On-Chip Hardware
A. Gordon-Ross, F. Vahid, IEEE Transactions on Computing - Best of
the 2003 MICRO and CASES conferences special issue. Special
Issue-Embedded Systems, Microarchitecture, and Compilation Techniques,
in Memory of B. Ramakrishna (Bob) Rau, Oct. 2005, Vol. 54, Issue 10,
pp 1203-1215. pdf
2003
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Tiny Instruction Caches For Low Power Embedded Systems
A. Gordon-Ross, S. Cotterell, F. Vahid,
ACM Transactions on Embedded Computing Systems, Vol. 2, Issue 4, Nov. 2003, pp. 449-481.
pdf
2002
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Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
A. Gordon-Ross, S. Cotterell, F. Vahid, IEEE Computer Architecture Letters,
Vol I, January 2002.
pdf
Book Chapter
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Tuning caches to applications for low-energy embedded systems
A. Gordon-Ross, C. Zhang, F. Vahid. N. Dutt, Chapter 6 in Ultra Low-Power
Electronics and Design - Kluwer Academic Pub, June 2004.
pdf
Technical Reports
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Fast Configurable-Cache Tuning with a Unified Second-Level Cache
A. Gordon-Ross, F. Vahid, N. Dutt. Technical Reprort UCR-CS-2005-05002, May 2005.
pdf
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Automatic Tuning of Two-Level Caches to Embedded Applications
A. Gordon-Ross, F. Vahid, N. Dutt Technical Report UCR-CSE-03-02, September 2003
pdf
Talks
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Low Power and Dynamic Optimizations Techniques for Power-Constrained Domains
- External Board Meeting, April 24, 2008
Hot Caches, Cool Techniques: Online Tuning of Highly Configurable Caches for Reduced
Energy Consumption
- March 2007.